Electronic switched-mode DC to DC converters convert one direct current (DC) voltage level to another, by storing the input energy temporarily and then releasing that energy to the output at a different voltage. The storage may be in either magnetic field storage components (inductors, transformers) and/or electric field storage components (capacitors). This conversion method is more power efficient (often 75% to 98%) than linear voltage regulation (which dissipates unwanted power as heat). Efficiency has increased due to the use of power field effect transistors (FETs), which are able to switch at high frequency more efficiently than power bipolar transistors (BJTs). BJTs incur more switching losses and require a more complicated drive circuit.
A buck converter is a voltage step down and current step up converter. In its simplest form, a buck converter comprises two switches and an inductor in series with a load. It controls the current in the inductor by the two switches (usually a transistor and a diode). Heuristically, the buck converter is best understood in terms of the relation between current and voltage of the inductor. Beginning with the switch open (i.e., in the off position), the current in the circuit is 0. When the switch is first closed, the current will begin to increase, and the inductor will produce an opposing voltage across its terminals in response to the changing current. This voltage drop counteracts the voltage of the source and therefore reduces the net voltage across the load.
Over time, the rate of change of current decreases, and the voltage across the inductor also then decreases, increasing the voltage at the load. During this time, the inductor is storing energy in the form of a magnetic field. If the switch is opened while the current is still changing, then there will always be a voltage drop across the inductor. So, the net voltage at the load will always be less than the input voltage source.
When the switch is opened again, the voltage source will be removed from the circuit, and the current will decrease. The changing current will produce a change in voltage across the inductor, now aiding the source voltage. The stored energy in the inductor's magnetic field supports current flow through the load. During this time, the inductor is discharging its stored energy into the rest of the circuit. If the switch is closed again before the inductor fully discharges, the voltage at the load will always be greater than zero.
Switched inductor, DC-DC down-converters, and buck converters provide conversion of power from one potential to another lower voltage potential. These types of converters are used in a broad and diverse set of applications. One typical application is the conversion and regulation of power supplies for microprocessors and other sensitive or high performance integrated circuits.
Modern integrated circuits using advanced complementary metal oxide semiconductor (CMOS) technology run on power supplies with voltages at 1V or less, while the power levels delivered to a computer are typically at 120V or higher. The power is down-converted in the computer from 120V AC to 1V DC for the microprocessor through a series of power converters. AC-DC converters will generally provide a range of DC voltages such as 3.3V, 5V and 12V, and then a buck converter will take one of those power levels and down-convert to the 1V required by the microprocessor.
Some buck converters down-convert power by driving a low pass filter with a pulse width modulation (PWM) signal. The low pass filter comprises an inductor in series with a capacitor, which is in parallel with the load. PWM signals are rectangular pulse wave trains whose pulse width is modulated resulting in a variation of the average value of the waveform. The PWM signal is produced by power switches or transistors that modulate a DC signal by connecting the input inductor terminal to either the input power supply (DC) or ground.
In the idealized converter, all the components are considered to be perfect. Specifically, the switch and the diode have zero voltage drop when on and zero current flow when off and the inductor has zero series resistance. Further, it is assumed that the input and output voltages do not change over the course of a cycle (this would imply that the output capacitance is infinite).
Typical buck converters have some physical separation from the load that they are powering. The physical separation results in an unwanted parasitic inductance and resistance between the output of the buck converter and the load. In the event of a load current transient, the high frequency content of that transient will see high impedance due to the parasitic inductance, and consequently there will be a large deviation in the voltage of that power supply.
FIG. 1 illustrates a schematic view of an exemplary power conversion system 10 according to the prior art. The system 10 includes a buck converter chip 110 with voltage sensing feedback loop 130. Buck converter chip 110 comprises feedback controller 120, n-type metal oxide semiconductor field effect transistor (NMOS transistor) 180, p-type metal oxide semiconductor field effect transistor (PMOS transistor) 170, series inductor 140, and shunt capacitor 150.
In concert, NMOS 180 and PMOS 170 transistors are comprised by a complementary metal oxide semiconductor (CMOS) device. As is customary in the art, NMOS transistor 180 source 182 is tied to ground 185, and PMOS transistor 170 source 172 is tied to input power (VS). NMOS transistor 180 drain 184 is in electrical communication with PMOS transistor 170 drain 174 and CMOS output 165 (bridge voltage Vb), as illustrated in FIG. 1. PMOS 170 and NMOS 180 transistor gates are electrically controlled by feedback controller 120. In one or more embodiments, PMOS 170 and NMOS 180 transistor gates are tied together in a traditional CMOS device configuration.
By opening and closing PMOS 170 and NMOS 180 transistor gates in a periodic, binary clock cycle, feedback controller 120 generates a pulse width modulation (PWM) signal at the CMOS device output 165. When PMOS transistor 170 is open, NMOS transistor 180 is closed and vice-versa, thereby engendering square wave form at the bridge voltage Vb. Feedback controller 120 modulates the width (on time) of the signal train giving rise to the PWM signal. Width determination (i.e., duty cycle) by feedback controller 120 is discussed in greater detail later in the disclosure.
PWM signal drives current though series inductor 140 at the bridge voltage Vb. The second terminal 145 of series inductor 140 is wired to buck converter chip output voltage and shunt capacitor 150 in parallel. As can be appreciated by one skilled in the art, the present configuration creates a low pass filter at the buck converter chip output voltage assuming a resistive load thereto, at least in part. The fundamental frequency of the PWM signal generated by the PMOS 170 and NMOS 180 transistor gates is configured to be much higher than the LC resonance of the output low pass filter formed by series inductor 140 and shunt capacitor 150. Consequently, the output of the filter is the average value of the switching signal, which is equal to the voltage of the input power supply Vs multiplied by the duty cycle of the PWM signal.
Power conversion system 100 incorporates feedback control through voltage sensing loop 130 of the buck converter chip 110. Measured at load 190, feedback control keeps a constant output voltage Vo (or approximately constant output voltage Vo such as within 5% or 10% or 15%) at load 190 with changing operating conditions such as input voltage (Vs) or load 190 current. At frequencies above the LC resonance, shunt capacitor 150 provides a low output impedance (Zout) which maintains the output voltage Vo during load 190 current transients. At frequencies below the LC resonance, the feedback controller 120 will modulate the buck converter's duty cycle to keep the output voltage Vo static during load 190 current transients.
Ideally, these components are lossless, which would result in near 100% conversion efficiency for the buck converter chip 110. In reality, series resistance in the series inductor 140, shunt capacitor 150 and switches (NMOS 170, PMOS 180 transistors) all result in loss. Similarly, parasitic capacitance in the series inductor 140 and capacitive switching losses from the switches (NMOS 170, PMOS 180 transistor gates) also result in inefficiency. Moreover, parasitic inductance 160 occurs along the wiring or power delivery channel (e.g., circuit trace elements) from the buck converter chip 110 output 115 to the load 190 which also detrimentally affects the desired functionality of the power conversion system 10. Accordingly, there is need in the art to provide for an efficient, regulated power supply which ameliorates the effects of parasitic inductance 160 et al.
FIG. 2 is a graphical plot representing a frequency response 20 of an exemplary buck converter without feedback control according to the prior art. Open loop output impedance (Zout-open) 21 is graphed as a function of frequency ω 24. The frequency response 20 of the buck converter indicates how the output voltage will change in response to changes in load current at a particular load frequency. (Those in the art may recognize the similarity to the transfer function plot, |H(jω)|.)
Ideally, the output impedance Zout-open is flat and very low, thereby maximizing the power transfer to the load in linear manner with respect to frequency. Frequency response 20 is an approximate, graphical representation of a buck converter without parasitic inductance between the buck converter and load. The output impedance Zout-open here is set by the buck converter inductor and capacitor and inductor series resistance. With reference to FIG. 2, peak 23 is located at resonant frequency ωr=1/√(LC). Low pass response 25 rises to meet peak 23. It can be observed that peak 23 drops off dramatically at the slope of the higher frequency response 22.
FIG. 3 is a graphical plot representing a frequency response 30 of an exemplary buck converter with some feedback control according to the prior art. Closed loop output impedance (Zout-closed) 31 is graphed as a function of frequency ω 34. With the feedback controller for the buck converter in operation, higher impedance at peak 33 (contrast to peak 23 of FIG. 2) is counteracted by feedback controller to provide a more desirable output impedance Zout-closed. Low pass response 35 remains flat as a function of frequency ω 34; however, the area integrated under peak 33 is smaller.
FIG. 4 is a graphical plot representing a frequency response 40 of an exemplary buck converter with some feedback control and parasitic inductance according to the prior art. Load impedance (Zload) 41 is graphed as a function of frequency ω 44. Up until peak 43, low pass response 45 is similar to that shown in FIG. 3, with the feedback controller for the buck converter in operation by counteracting the higher impedance. Peak 43 corresponds to the LC resonance frequency discussed above.
Turning to FIG. 4, the impedance at the load Zload is shown with the parasitic inductance between the buck converter chip output and the load. As a result, parasitic inductance causes the output impedance Zload to increase at higher frequencies (see high frequency response 42), despite the low output impedance provided by the output capacitor in the buck converter.
With the development of highly integrated electronic systems that consume large amounts of electricity in very small areas, the need arises for new technologies that enable improved energy efficiency and power management for future integrated systems. Integrated power conversion is a promising potential solution as power can be delivered to integrated circuits at higher voltage levels and lower current levels. That is, integrated power conversion allows for step down voltage transformers to be disposed in close proximity to transistor elements.
Accordingly, there is a need for high quality inductors to be used in large scale CMOS integration. This provides a platform for the advancement of systems comprising highly granular dynamic voltage and frequency scaling as well as augmented energy efficiency. The present disclosure contemplates the novel fabrication of efficient and compact on-chip, high bandwidth power converters and practical methods for manufacturing operating thereof for remedying these and/or other associated problems.